Modern x86: AVX tour

YMM registers

AVX (2011) widens the vector registers to 256 bits: YMM0-YMM15, each holding eight floats or four doubles. AVX2 adds integer vector operations, and AVX-512 widens again to ZMM - present on server chips and recent desktops.

vmovaps ymm0, [a] vmovaps ymm1, [b] vaddps ymm0, ymm0, ymm1 ; eight float adds vmovaps [sum], ymm0

The VEX forms

AVX instructions start with V (vaddps, vmulpd, vmovaps) and take three operands: destination, source1, source2. The three-operand form means the destination is separate from the inputs, so the accumulator pattern needs no extra moves.

Checking CPU support

CPUID reports AVX in ECX bit 28 of leaf 1, and AVX2 in EBX bit 5 of leaf 7. Real programs check before running vector code and fall back to SSE or scalar. The align 16 directive becomes align 32 for AVX data.

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Article author: Arthur Isaev