ARM assembly

Registers

AArch64 has thirty-one 64-bit general registers (X0-X30), a stack pointer (SP), and a zero register (XZR, always zero). W0-W30 are the 32-bit views. There are no flags for most instructions: comparisons produce a condition code in dedicated status registers.

mov x0, 1 ; like mov edi, 1 on x86 add x1, x0, x0 ; x1 = x0 + x0 cbz x0, skip ; branch if x0 is zero

Conditional execution

Classic ARM (32-bit) could suffix almost every instruction with a condition (ADDEQ, MOVNE). AArch64 dropped that in favor of conditional selects (CSEL) and compare-and-branch (CBZ, CBNZ), which the compiler emits for short if/else chains.

Syscalls on Linux ARM

On AArch64 Linux, the syscall number goes in X8 and arguments in X0-X5, and the SVC (supervisor call) instruction enters the kernel with 0 as the argument. The numbers differ from x86-64: write is 64 and exit is 93. Everything else - sections, labels, the linker - works the same as this course.

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Article author: Arthur Isaev